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  obsolescence notice this product is obsolete. this information is available for your convenience only. for more information on zarlink?s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/
ma5104 1 ds3580-3.2 the ma5104 4k static ram is configured as 4096 x 1 bits and manufactured using cmos-sos high performance, radiation hard, 3 m m technology. the device has separate input and output terminals controlled by chip select and write enable. the design uses a 6 transistor cell and has full static operation with no clock or timing strobe required. address input buffers are deselected when chip select is in the high state. features n 3 m m cmos-sos technology n latch-up free n fast access time 90ns typical n total dose 10 6 rad(si) n transient upset >10 10 rad(si)/sec n seu <10 -10 errors/bitday n single 5v supply n three state output n low standby current 10 m a typical n -55 c to +125 c operation n all inputs and outputs fully ttl or cmos compatible n fully static operation ma5104 radiation hard 4096 x 1 bit static ram figure 2: block diagram operation mode cs we i/o power read l h d out isb1 write l l d in standby h x high z isb2 figure 1: truth table april 1995
ma5104 2 symbol parameter min. max. units v cc supply voltage -0.5 7 v v i input voltage -0.3 v dd +0.3 v t a operating temperature -55 125 c t s storage temperature -65 150 c figure 3: absolute maximum ratings stresses above those listed may cause permanent damage to the device. this is a stress rating only and functlonal operation of the device at these condltions, or at any other condition above those indicated in the operations section of this specification, is not implied exposure to absolute maxlmum rating conditions for extended perlods may affect device reliability. notes for tables 4 and 5: 1. characteristics apply to pre radiation at t a = -55 c to +125 c with v dd = 5v 10% and to post 100k rad(si) total dose radiation at t a = 25 c with v dd = 5v 10% (characteristics at higher radiation levels available on request). 2. worst case at t a = +125 c, guaranteed but not tested at t a = -55 c. group a subgroups 1, 2, 3. symbol parameter conditions min. typ. max. units v dd supply voltage - 4.5 5.0 5.5 v v lh input high voltage - v dd /2 - v dd v v ll input low voltage - v ss - 0.8 v v oh output high voltage i oh1 = -1ma 2.4 - - v v ol output low voltage i ol = 2ma - - 0.4 v i li input leakage current (note 2) all inputs except cs -- 10 m a i lo output leakage current (note 2) output disabled, v out = v ss or v dd -- 20 m a i pui input pull-up current v in = v ss on cs input only - - -100 m a i pdi input leakage current v in = v ss on cs input only - - 5 m a i dd power supply current f rc = 1mhz, cs = 50% mark:space - 12 16 ma i sb1 selected supply current cs = v ss -2535ma i sb2 standby supply current chip disabled - 50 3000 m a figure 4: electrical characteristics symbol parameter conditions min. typ. max. units v dr v cc for data retention cs = v dr 2.0 - - v i ddr data retention current cs = v dr , v dr = 2.0v - 30 2000 m a figure 5: data retention characteristics characteristics and ratings
ma5104 3 ac characteristics conditions of test for tables 5 and 6: 1. input pulse = v ss to 3.0v. 2. times measurement reference level = 1.5v. 3. transition is measured at 500mv from steady state. 4. this parameter is sampled and not 100% tested. notes for tables 6 and 7: characteristics apply to pre-radiation at t a = -55 c to +125 c with v dd = 5v 10% and to post 100k rad(si) total dose radiation at t a = 25 c with v dd = 5v 10%. group a subgroups 9, 10, 11. symbol parameter min max units t avavr read cycle time 135 - ns t avqv address access time - 135 ns t elqv chip select to output valid - 135 ns t elqx (4) chip select to output active 10 - ns t elqz (4) chip select to output tri state 10 50 ns t axqx output hold from address change 10 - ns figure 6: read cycle ac electrical characteristics symbol parameter min max units t avavw write cycle tlme 135 - ns t avwl address set up time 10 - ns t wlwh write pulse width 50 - ns t whav write recovery time 5 - ns t dvwh data set up time 35 - ns t nhdx data hold time 5 - ns t wlqz (4) write enable to output tri state 10 50 ns t elwl chip selection to write low 25 - ns t elwh chip selection to end of write 85 - ns t avwh address valid to end of write 80 - ns t whqx (4) output active from end to write 5 - ns figure 7: write cycle ac electrical characteristics symbol parameter conditions min. typ. max. units c in input capacitance v l = 0v - 6 10 pf c out output capacitance v o = 0v - 8 12 pf note: t a = 25 c and f = 1mhz. data obtained by characterisation or analysis; not routinely measured. figure 8: capacitance
ma5104 4 symbol parameter conditions f t basic functionality v dd = 4.5v - 5.5v, freq = 1mhz v il = v ss , v ih = v dd , v ol 1.5v, v oh 3 1.5v temp = -55 c to +125 c, gps pattern set group a subgroups 7, 8a, 8b figure 9: functionality subgroup definition 1 static characteristics specified in tables 4 and 5 at +25 c 2 static characteristics specified in tables 4 and 5 at +125 c 3 static characteristics specified in tables 4 and 5 at -55 c 7 functional characteristics specified in table 9 at +25 c 8a functional characteristics specified in table 9 at +125 c 8b functional characteristics specified in table 9 at -55 c 9 switching characteristics specified in tables 6 and 7 at +25 c 10 switching characteristics specified in tables 6 and 7 at +125 c 11 switching characteristics specified in tables 6 and 7 at -55 c figure 10: definition of subgroups
ma5104 5 timing diagrams figure 11a: read cycle 1 1. we is high for read cycle. 2. address vaild prior to or coincident with cs transition low. figure 11b: read cycle 2 t avavr t avqv t axqx address data out data valid 1. we is high for read cycle. 2. device is continually selected. cs low. t avavr t avqv t axqx t elqv t elqx t ehqz address cs data out high impedance data valid
ma5104 6 figure 12: write cycle 1. we must be high during all address transitions. 2. a write occurs during the overlap (t wlwh ) of a low cs , a high ce and a low we . 3. t whav is measured from either cs or we going high or ce going low, whichever is the earlier, to the end of the write cycle. 4. if the cs low transition occurs simultaneously with, or after, the we low transition, the output remains in the high impedance state. 5. data out is the write data of the current cycle, if selected. 6. data out is the read data of the next address,if selected. 7. t elwl must be met to prevent memory corruption. address t avavw t avwh t avwl t wlwh (2) t whav (3) t elwl (7) (4) t wlqz we t axqx t wlqh data out (5) (6) high impedance data valid data in t dvwh t whdx t elwh cs
ma5104 7 outlines and pin assignments figure 13: 18-lead ceramic dil (solder seal) - package style c ref millimetres inches min. nom. max. min. nom. max. a - - 5.715 - - 0.225 a1 0.38 - 1.53 0.015 - 0.060 b 0.35 - 0.59 0.014 - 0.023 c 0.20 - 0.36 0.008 - 0.014 d - - 23.11 - - 0.910 e - 2.54 typ. - - 0.100 typ. - e1 - 8.13 typ. - - 0.300 typ. - h 4.44 - 5.38 0.175 - 0.212 me - - 8.28 - - 0.326 z - - 1.27 - - 0.050 w - - 1.53 - - 0.060 xg406 d w a e b z h a 1 15 m e c e 1 seating plane 1 9 18 10 18 vdd 17 a6 16 a7 15 a8 14 a9 13 a10 12 a11 11 din 10 cs 1 a0 2 a1 3 a2 4 a3 5 a4 6 a5 7 dout 8 we 9 vss top view
ma5104 8 figure 14: 24-lead ceramic flatpack (solder seal) - package style f 1nc 2a0 3a1 4a2 5a3 6a4 7a5 8 dout 9nc 10 we 11 vss 12 nc 24 vdd 23 a6 22 a7 21 a8 20 nc 19 nc 18 a9 17 a10 16 a11 15 din 14 nc 13 cs bottom view ref inches min. nom. max. a - - 0.105 a1 0.026 - - b 0.015 - 0.019 c 0.003 - 0.006 d 0.590 - 0.610 e - 0.050 - l 0.265 - 0.305 m 0.395 - 0.405 me 0.30 - - z 0.005 - 0.045 xg537 m b e d l a a1 c pin 1 z m e
ma5104 9 figure 15: burnin and radiation configuration package option burnin function f c via static 1 static 2 dynamic radiation a0 2 1 r 0v 5v f0 5v a1 3 2 r 0v 5v f1 5v a2 4 3 r 0v 5v f2 5v a3 5 4 r 0v 5v f3 5v a4 6 5 r 0v 5v f4 5v a5 7 6 r 0v 5v f5 5v dout 8 7 r 0v 5v load 5v web 10 8 r 0v 5v f12 5v vss 11 9 direct 0v 0v 0v 0v csb 13 10 r 0v 5v 0v 5v din 15 11 r 0v 5v f13 5v a11 16 12 r 0v 5v f11 5v a10 17 13 r 0v 5v f10 5v a9 18 14 r 0v 5v f9 5v a8 21 15 r 0v 5v f8 5v a7 22 16 r 0v 5v f7 5v a6 23 17 r 0v 5v f6 5v vdd 24 18 direct 5v 5v 5v 5v 1. f0=150khz, f1=f0/2, f2=f0/4, f3=f0/8 etc. 2. burnin r=1k 3. radiation r=10k
ma5104 10 radiation tolerance total dose radiation testing for product procured to guaranteed total dose radiation levels, each wafer lot will be approved when all sample devices from each lot pass the total dose radiation test. the sample devices will be subjected to the total dose radiation level (cobalt-60 source), defined by the ordering code, and must continue to meet the electrical parameters specified in the data sheet. electrical tests, pre and post irradiation, will be read and recorded. gec plessey semiconductors can provide radiation testing compliant with mil-std-883 test method 1019, ionizing radiation (total dose). ion let (mev.cm 2 /mg) upset bit cross-section (cm 2 /bit) figure 17: typical per-bit upset cross-section vs ion let single event upset characteristics total dose (function to specification)* 1x10 5 rad(si) transient upset (stored data loss) 5x10 10 rad(si)/sec transient upset (survivability) >1x10 12 rad(si)/sec neutron hardness (function to specification) >1x10 15 n/cm 2 single event upset** 3.4x10 -9 errors/bit day latch up not possible * other total dose radiation levels available on request ** worst case galactic cosmic ray upset - interplanetary/high altitude orbit figure 16: radiation hardness parameters
ma5104 11 ordering information for details of reliability, qa/qc, test and assembly options, see manufacturing capability and quality assurance standards section 9. unique circuit designator s l c r radiation hard processing 30 krads (si) guaranteed 50 krads (si) guaranteed 100 krads (si) guaranteed radiation tolerance c f ceramic dil (solder seal) flatpack (solder seal) package type qa/qci process (see section 9 part 4) test process (see section 9 part 3) assembly process (see section 9 part 2) l c d e b s rel 0 rel 1 rel 2 rel 3/4/5/stack class b class s reliability level max5104xxxxx headquarters operations gec plessey semiconductors cheney manor, swindon, wiltshire, sn2 2qw, united kingdom. tel: (01793) 518000 fax: (01793) 518411 gec plessey semiconductors p.o. box 660017, 1500 green hills road, scotts valley, california 95067-0017, united states of america. tel: (408) 438 2900 fax: (408) 438 5576 customer service centres ? france & benelux les ulis cedex tel: (1) 64 46 23 45 fax: (1) 64 46 06 07 ? germany munich tel: (089) 3609 06-0 fax: (089) 3609 06-55 ? italy milan tel: (02) 66040867 fax: (02) 66040993 ? japan tokyo tel: (03) 5276-5501 fax: (03) 5276-5510 ? north america scotts valley, usa tel: (408) 438 2900 fax: (408) 438 7023 ? south east asia singapore tel: (65) 3827708 fax: (65) 3828872 ? sweden stockholm tel: 46 8 702 97 70 fax: 46 8 640 47 36 ? taiwan, roc taipei tel: 886 2 5461260 fax: 886 2 7190260 ? uk, eire, denmark, finland & norway swindon, uk tel: (01793) 518527/518566 fax: (01793) 518582 these are supported by agents and distributors in major countries world-wide. ? gec plessey semiconductors 1995 publication no. ds3580-3.2 april 1995 technical documentation - not for resale. printed in united kingdom. this publication is issued to provide information only which (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. the company reserves the right to alter without prior knowledge the specification, design or price of any product or s ervice. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it i s the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services prov ided subject to the company's conditions of sale, which are available on request.


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